Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits 2nd Edition /
Guardado en:
| Autor Principal: | |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | |
| Formato: | Electrónico |
| Idioma: | English |
| Publicado: |
Boston, MA :
Springer,
2007.
|
| Series: | Frontiers in Electronic Testing,
34 |
| Materias: | |
| Acceso en línea: | SpringerLink, via BECYT |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
| LEADER | 01074nmm a22003015u 4500 | ||
|---|---|---|---|
| 001 | springer.978-0-387-46546-3 | ||
| 003 | Springer | ||
| 005 | 20100326162152.0 | ||
| 007 | cr#nn#008mamaa | ||
| 008 | 100301s2007 xx j eng#d | ||
| 020 | |a 9780387465470 | ||
| 100 | 1 | |a Sachdev, Manoj. | |
| 245 | 1 | 0 | |a Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits |h [electronic resource] : |b 2nd Edition / |c edited by Manoj Sachdev, José Pineda de Gyvez. |
| 260 | |a Boston, MA : |b Springer, |c 2007. | ||
| 300 | |b v.: digital | ||
| 440 | 0 | |a Frontiers in Electronic Testing, |x 0929-1296 ; |v 34 | |
| 650 | 0 | |a Engineering | |
| 650 | 0 | |a Engineering design | |
| 650 | 0 | |a Electronics | |
| 650 | 0 | |a Systems engineering | |
| 650 | 1 | 4 | |a Engineering |
| 650 | 2 | 4 | |a Circuits and Systems |
| 650 | 2 | 4 | |a Electronic and Computer Engineering |
| 650 | 2 | 4 | |a Engineering Design |
| 650 | 2 | 4 | |a Electronics and Microelectronics, Instrumentation |
| 700 | 1 | |a Gyvez, José Pineda de. | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 856 | 4 | 0 | |u http://dx.doi.org/10.1007/0-387-46547-2 |y SpringerLink, via BECYT |